1. Field of the Invention
The present invention generally relates to a method for manufacturing a semiconductor device. More specifically, the present invention is directed to a resist pattern forming method used in manufacturing of a semiconductor integrated circuit element, and in particular, to a resist pattern forming method capable of effectively achieving high alignment precision by drawing a wiring pattern and a contact hole pattern on the same photomask (reticle) and by using this photomask several times to perform an exposing process.
2. Description of the Related Art
Very recently, when semiconductor integrated circuits (semiconductor devices) are manufactured, underlayers such as semiconductor substrates are selectively processed by executing etching processes and ion implantations. In this case, in order to selectively protect non-processed portions of the underlayers, patterns of composite materials being photosensed by active light rays such as ultraviolet rays, X-rays, and electron beams, so-called "photosensitive resist film" (will be referred as "resist" hereinafter) are formed on the underlayers.
In the most general method for forming the resist patterns, the ultraviolet ray irradiating method is employed by using the reduced projection exposing apparatus (stepper) in which the light source is constructed of g-ray (wavelength=436 nm) of a mercury lamp, i-ray (wavelength=365 nm), or KrF excimer laser light (wavelength=248 nm).
In the stepper, the photomask is mounted to execute the exposing process. This photomask is called as a "reticle" in which a circuit pattern is formed on a glass substrate by a shield film such as chromium(Cr). During the exposing operation, precise positioning (alignment) must be carried out in order that the mutual positional relationship between the photomask and the previously formed circuit pattern on the substrate.
The pattern drawn on the photomask is reduced through the lens and transferred to the resist film coated on the semiconductor substrate. Thereafter, this resist film is developed, so that the resist pattern can be formed.
There are a positive type resist and a negative type resist. The positive type resist is such a resist that a light irradiated portion is soluble by a developing fluid, but a light non-irradiated portion is insoluble. The negative type resist is such a resist that a light irradiated portion is not insoluble by a developing fluid, but a light non-irradiated portion is soluble.
To manufacture a semiconductor integrated circuit device, this resist pattern forming stage is normally required 20 to 30 times.
Currently, semiconductor integrated circuits are rapidly integrated in high degrees and are made with high performance. In connection with this trend, strong demands are further made by that the circuit patterns are made narrower. As an example of a DRAM (dynamic random access memory), a resist pattern with a level of 0.4 .mu.m is drawn in 16 Mbits DRAM manufactured in mass production. In this photolithography stages, i-rays among ultraviolet rays are mostly utilized. Also, resist patterns with levels of 0.35 to 0.30 .mu.m are required in 64 Mbits DRAM under transition stage from trial to mass production. Further, resist patterns with levels smaller than 0.25 .mu.m are required in 256 Mbits DRAM and 1 Gbit DRAM under developing/examination trial stages. It is conceivable that KrF excimer laser light can be effectively utilized. Also, the dimension precision and the alignment precision must be increased in conjunction with fine widths of patterns.
For instance, in a semiconductor device having a level related to 256 Mbits DRAM, the dimension control of approximately .+-.0.03 .mu.m is required, and the alignment precision of approximately 0.06 .mu.m is required with respect to the respective stages. This dimensional requirement may be more strictly required in future.
The factors of the alignment precision deterioration are caused by magnification errors in an exposure lens, rotation errors occurred between a reticle and a chip formed on a wafer, and errors occurred during alignment measurements. Each of the precision may be gradually increased by improving the performance of the lens and the wafer stage of the exposing apparatus, and the performance of the alignment measuring apparatus.
Then, when the required precision of the alignment error is strictly increased, the reticle manufacturing error cannot be neglected. Moreover, when the integration degree is increased, the drawing area and the figure data number are increased. Therefore, the time required to draw the patterns by the electron beams (EB) is greatly prolonged during the reticle manufacture. The errors produced when the reticle is manufactured can be hardly suppressed due to such adverse influences by coating the resist, developing the resist, and by the surface uniform characteristic of the etching process.
Next, a description will now be made of the conventional pattern forming method with employment of a single reticle per one step.
First, in FIG. 58A, there is shown a first reticle (photomask) 101 used when a pattern of a contact hole is exposed. Within this first reticle 101, a contact hole pattern 102 is drawing by electron beams to be formed. Also, in FIG. 58B, there is represented a second reticle 103 used when patterns of a wiring line electrically connected to a contact and of other wiring lines are exposed. In this second reticle 103, wiring patterns 104a and 104b are formed by a light shielding portion. A width of a portion of the wiring pattern 104a becomes wide among these wiring patterns. This wide portion is a connection portion with a contact, and is designed to be a large dimension due to an allowance.
Next, one example of the method for manufacturing the semiconductor device is represented. In this method, as shown in FIG. 59, a stacked insulating film 107 is opened in an active region 106 on a surface of a semiconductor substrate 105. The following description is made of such cases that a contact 108 is formed so as to be buried within the opening, an upper layer wiring line 109 in contact with this contact 108 is formed, and a wiring line 109b is formed on the insulating film 107.
First, as illustrated in FIG. 60, a silicon oxide film 107 having a thickness of on the order of 5000 .ANG. is stacked on the semiconductor substrate 105 on which the active region 106 is partially formed. Next, the commercially available positive type resist film having a thickness of on the order of 5000 .ANG. is coated. Then, an exposing process is carried out be employing a KrF excimer laser (wavelength being 248 nm) 111 as a light source via a first reticle 101 on which the contact hole pattern 102 shown in FIG. 58A is formed.
Exposure energy required in this exposing process is 60 mj/cm.sup.2.
Next, as indicated in FIG. 61, the baking process (PEB) is performed after the exposing process for 90 seconds under temperature of 110.degree. C., and then the developing process is carried out for 60 seconds by using a 2.38 weight % solution of tetrametyle alchole ammonium hydroxide (TMAH). Thus, a resist pattern 110b having an opening portion 110a is obtained.
Thereafter, as indicated in FIG. 62, while using the resist pattern 110b as an etching mask, the anisotropic etching process is carried out with respect to the silicon oxide film 107, so that a contact hole 108a is formed. At this stage, the active region 106 formed on the surface of the semiconductor substrate 1 may be made as a low resistance value by previously implanting the impurity ions.
Thereafter, as shown in FIG. 63, the resist pattern 110b is removed by way of the oxygen plasma ashing method. It should be understood that the above-described ion implanting operation may be carried out at this stage.
Next, as shown in FIG. 64, a metal wiring material 109 such as tungsten silicide (WSi.sub.2) is stacked with having a thickness of approximately 1000 .ANG. by way of the sputtering method, or the CVD (chemical vapor deposition) method. At this time, the contact hole 108a is filled with the metal wiring material 109 to form the contact 108.
Thereafter, as shown in FIG. 65, a positive type resist film 112 is coated on the entire surface of the metal wiring material. Then, the exposing process is carried out by employing the KrF excimer laser stepper via the second reticle 103 on which the wiring patterns 104a and 104b are drawn, as shown in FIG. 58B. At this time, the necessary exposure energy is 35 mj/cm.sup.2.
Next, as indicated in FIG. 66, the PEB process and the developing process are carried out to thereby form a resist pattern 112a. A portion from which the photoresist has been removed by the developing process is used as an opening portion 112b.
Thereafter, as shown in FIG. 67, while using the resist pattern 112a as an etching mask, the anisotropic etching operation is carried out with respect to the metal wiring material 109. Then, the metal wiring material 109 is formed into predetermined wiring lines 109a and 109b.
Next, the resist pattern 112a is removed, so that a semiconductor device as shown in FIG. 59 can be manufactured.
In such a case that the patterns are formed in accordance with the above-described manner, since the semiconductor device is manufactured by employing two sets of the reticles, namely the first reticle 101 on which the contact hole pattern 102 is formed, and the second reticle 103 on which the wiring pattern 104 is formed, there are adverse influences caused by the manufacturing errors of the reticles. In other words, the reticles on which the patterns are drawn by the electron beams are adversely influenced when the patterns are drawn due to the following factors, namely, the stage precision of the EB drawing apparatus, the positional precision of the beams under scanning, the temperatures in the apparatus, the adhesive conditions of the deposited articles within the column of the apparatus, the bend of the blanks (glass substrate) of the reticles, and the like. Therefore, the positional precision of the patterns drawn on the reticles is deteriorated.
Accordingly, when this conventional method is used to manufacture, for instance, the semiconductor device with the level of 256 Mbits DRAM, the alignment error caused by the manufacturing errors between the reticles becomes on the order of 10 to 20 nm on the wafer.
FIG. 68 represents a positional relationship between the contact 108 and the wiring line 109a in such a case that the alignment error occurs during the photolithography. In FIG. 68, symbol X.sub.1 indicates a region where an opening pattern should be originally arranged, and symbol X.sub.2 shows a region occupied by the opening pattern when the alignment error occurs. A shift between X.sub.1 and X.sub.2 denotes a portion indicated by a symbol Y.sub.1. As shown in FIG. 68, when the wiring line is patterned under such a condition that the alignment error occurs, such a wiring line containing a pattern shift Y.sub.2 (see FIG. 69) would be eventually formed.
Although the pattern shift Y.sub.2 is produced along the sectional direction in this example, other various cases may be conceived, for example, the pattern shift is produced along the longitudinal direction. Since such a pattern shift is produced, the matching characteristic with respect to the pattern in the upper layer is deteriorated. Therefore, this may cause the contact failure and the shortcircuits in the wiring lines.
As another conventional method, Japanese Unexamined Paten Publication No.63-313866 discloses the method for forming the resist patterns with the different shapes by employing the same reticle (photomask) on which the patterns having the different sizes are drawn.
According to this conventional method, one resist pattern forming method is similar to the normal resist pattern forming method such that the exposing process is carried out with respect to the resist film via one sheet of the reticle, and the developing process is performed to thereby obtain the resist pattern. Another method for forming the resist patterns with the different shapes is accomplished by that after the above-explained normal resist pattern has been formed by using the same reticle, the thermal process at a preselected temperature is carried out so as to deform (thermally melt) the resist. The resist is caused to flow into a narrow interval (space) portion between the resist patterns to thereby fill the opening portion. To the contrary, as to a wide interval portion between the resist patterns, this opening condition is maintained. Then, only the large pattern (namely, pattern having large area) is formed. After the normal resist pattern is formed, the shapes of the resist patterns are made different by performing either the thermal process or not performing the thermal process.
However, in such a case that the resist pattern is deformed so as to vary the shapes of the resist pattern, the dimensions of the finally obtained resist patterns are slightly fluctuated by the film thickness of the resist film, and the changes in the temperature. Such a problem is conceivable that the process operation can be hardly performed in high precision.